Selective snooping by snoop masters to locate updated data

ABSTRACT

A system and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has a cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in an non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 10/393,116, now U.S. Pat. No. 7,395,380 filed Mar. 20, 2003.

FIELD OF THE INVENTION

This invention relates generally to cache memory snooping and, more particularly, to an improved technique for snooping hardware enforced cache coherency when at least one master on a bus has a cache and shares data within an address range with other masters.

BACKGROUND OF THE INVENTION

In a system wherein there are multiple devices that share a common main memory, and each can individually cache data from addresses in main memory, to ensure data consistency among devices, a mechanism often used is known as hardware enforced cache coherency of data. A portion of this mechanism is known as “snooping”. When a processor, or other snooping master, makes a coherent access to main memory, that access is first broadcast to all the other snooping masters (the “non-originating snooping masters”) as a “snoop request” by a central resource, called the “Bus Macro”. The non-originating snooping masters react to the snoop request by returning a snoop result that indicates the state of that master's cache for the address provided with the snoop request. The bus macro receives all the snoop results and takes one of several possible actions based on the values of the snoop results. One action may be to allow the main memory access to complete. Another action may be to delay the main memory access until the non-originating snooping masters write modified data from their caches back to main memory. Other actions are also possible. Note that the most common type of snooping master with a cache is a processor, although other devices, such as DMA controllers, can be used.

Typically, when memory coherence is required, all snooping masters continuously snoop all main memory accesses to ensure data consistency. However, there are often times when the originating master knows which non-originating snooping masters need to participate in the snooping of its request. In these cases, it is desirable not to broadcast the snoop request to the non-originating snooping masters that do not need to participate in the snoop. This is desirable for several reasons:

1) Unnecessary power is consumed making the snoop requests to non-originating snooping masters that do not need to receive the request.

2) Once the request is made to the non-originating snooping master, that snooping master must snoop its cache to see if it has a cached copy of the requested address location. This snooping of the cache may interfere with the non-originating snooping master from accessing the cache locally, thus decreasing the performance of the non-originating snooping master.

3) If one of the non-originating snooping masters takes many clock cycles to snoop its cache (e.g. because it is physically located across a bridge), the originating master will be stalled until the slowest non-originating snooping master has completed the snoop, thus decreasing the originating master's performance.

SUMMARY OF THE INVENTION

According to the present invention, a system and structure for snooping the cache memories of a plurality of snooping masters connected to a bus macro having snooping logic is provided. Each of the snooping masters has a cache memory and the cache memories of some, but less than all, of the snooping masters may have the data requested by an originating snooping master and, in the disclosed protocol, the needed data in only one non-originating snooping master is marked as updated. A main memory having addresses for all data is connected to the bus macro.

An originating snooping master through the bus macro queries only those non-originating snooping masters which may have the requested data. All the non-originating snooping masters that have been queried reply through the bus macro to the originating snooping master. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory through said bus macro. If none of the non-originating snooping masters have the requested data marked as updated, then the requested data is read from main memory by the bus macro, and then sent to the originating master.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high level diagram of a plurality of snooping masters and slave devices connected to a bus macro and arbiter; and

FIG. 2 is a flow diagram of the fulfillment of a snoop request that may be used in the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring now to the drawings, and for the present to FIG. 1, a high level block diagram of several snooping masters and several slave devices connected to a bus macro and arbiter are shown. As illustrated in FIG. 1, a plurality of snooping masters or bus masters 10 a, 10 b, 10 c, 10 d, 10 e . . . 10 n are shown. As indicated above, the snooping masters 10 a . . . 10 n normally include processors, but they also may include certain other types of bus masters. It is required that the snooping masters that are to be snooped have cache memories 12 a . . . 12 n and be connected to bus macro 14 through connections 16 a . . . 16 n. Although not shown, some masters may share a connection. (The bus macro 14 will sometimes be referred to simply as bus 14). Also shown are two slave devices in the form of main memory 18 and an I/O device 20. It is to be understood that more slave devices could be present. The main memory 18 and I/O device 20 are connected to slave control logic 22 on bus 14 through connections 24 and 26, respectively. The main memory 18 contains all the address locations that any master 10 a . . . 10 n may need. The snooping masters 10 a . . . 10 n are connected to snoop control logic 28 on bus 14 through connections 30 a . . . 30 n, respectively.

Referring now to FIG. 2, the operation of the present invention where a snooping master requires updated data is shown as a flow diagram. (In FIG. 2, those steps that are unique to this invention have the boxes in heavier outline, and those steps that are common to the prior art are in normal outline in the boxes.) The term “snooping”, as used herein, means a bus master which can query the cache memories of the non-originating bus masters for the data that the originating bus master needs and, if any of the non-originating bus masters 10 a . . . 10 n has such data which is updated, then the updated data is returned either directly or through main memory 18 to the originating bus master. There are many protocols that can be used in snooping, including but not limited to Modified Exclusive Shared Invalid (MESI), Modified Exclusive Invalid (MEI), Modified Exclusive Recent Shared Invalid (MERSI), and Modified Owned Shared Invalid (MOSI). The present invention will be described as it is implemented in MESI; however, it is to be understood that this invention is applicable to other protocols as well.

According to MESI, the protocol used in this scheme, only one master may have the data marked as updated. If no updated data is found in any of the non-originating snooping master's cache memory, the requested data is read from main memory 18 and written to the originating bus master.

As can be seen in FIG. 2, the first step 36 is for the originating master 10 a to check its own cache memory 12 a to see if updated data is there and marked with the desired state. The desired state for a write operation is Modified or Exclusive. The desired state for a read operation is Modified, Exclusive, or Shared. (In this illustration, master 10 a is assumed to be the originating master, and the masters 10 b . . . 10 n are assumed to be the non-originating snooping masters; however, any master 10 a . . . 10 n can be the originating master, and all the other masters 10 are then the non-originating snooping masters.) If at step 36 the originating master 10 a finds the desired data in its own cache memory 12 a in the desired state, then no snoop query is generated, the data found in cache memory 12 a is used by master 10 a and the process is done as shown in step 38. If, however, cache memory 12 a does not have the data in the desired state, then a snoop request is generated. According to the present invention, only those masters 10 b . . . 10 n that might have the requested data are snooped. This is referred to as targeted snooping. This has three beneficial effects over the prior art technique of snooping all non-originating snooping masters 10 b . . . 10 n, as follows:

1) power is saved by not querying any masters 10 b . . . 10 n that cannot have the requested data;

2) those masters that cannot have the data are not delayed from performing the task in which they might be engaged when a query is received; and

3) extra clock cycles are not unnecessarily incurred while waiting for snoop responses from long latency masters that cannot have the requested data, which will hold up the response time to the originating master.

In order to accomplish this limited or targeted query, a snoop mask is generated by the requested master as shown in step 40. Alternatively, this snoop mask could be generated by the bus macro and operate in the same manner. In another embodiment, the snoop mask could be generated by non-originating snooping masters, in which case the request would be sent to these non-originating snooping masters but their cache memory would not be queried and, thus, the request would not be acted on. Only the mask generation by the originating master will be described herein. Mask generation by the originating master is accomplished by the originating master 10 a knowing which non-originating snooping masters could potentially share the requested data. There are a variety of techniques by which the originating master could determine which non-originating snooping masters could potentially share the requested data. One such technique involves a program resident in each master 10 a . . . 10 n which “knows” what tasks each master 10 a . . . 10 n is performing and has performed From this information, the originating master 10 a can exclude those of masters 10 b . . . 10 n which would not have the requested data. The snoop mask may be represented in a multitude of ways. One such mechanism is a simple one bit flag for each non-originating master 10 b . . . 10 n, wherein a “1” indicates that that specific master 10 be queried, and a “0” indicates this specific master 10 not be queried. The originating master 10 a then conveys the snoop request to the bus 14, including the snoop mask created as shown in step 42. The bus 14 under the control of snooping logic 18 sends the snooping query to all designated (by the snoop mask) non-originating snooping masters 10 as shown in step 44. From this point on, the operation of the snooping is similar to the prior art as dictated by the particular protocol.

Each of the designated (by the snoop mask) non-originating masters 10 checks its cache memory 12 for the requested address of the data as shown in step 46, while the bus 14 waits for the designated non-originating masters 10 to respond as shown in step 48, and the main memory 18 waits for the bus 14 to read or write data as shown in step 50.

Each designated, non-originating master 10 responds to the bus 14 with its snoop results as to whether it has or does not have updated data as shown in step 52, and the bus 14 collects these results as shown in step 54. If one of the designated, non-originating masters 10 has updated data (it will be remembered that only one master 10 a . . . 10 n can have updated data so marked in this protocol), the updated data is sent to the bus 14 as shown in step 56. If updated data is sent to the bus 14, this updated data is sent by the bus 14 to the originating master 10 a and to main memory 18 as shown in step 62, the data in cache 12 a of the originating master 10 a conditionally being marked as updated. (It is to be understood that in some protocols the updated data may be sent only to the originating master 10 a or only to the main memory 18, or it may be sent indirectly to the originating master 10 a through the main memory 18 and read therefrom.) If none of the responses from the designated non-originating masters 10 is marked as updated in step 54, then data is read from the proper address in main memory 18 as shown in step 60 and sent to the bus 14 as shown in step 64, which sends the data from the main memory 18 to the originating master as shown in step 66 in this protocol. At this point, the snooping is completed.

While the invention has been described in combination with specific embodiments thereof, there are many alternatives, modifications, and variations that are likewise deemed to be within the scope thereof. Accordingly, the invention is intended to embrace all such alternatives, modifications and variations as fall within the spirit and scope of the appended claims. 

1. A computer system comprising: a bus and a plurality of snooping masters attached thereto to communicate with each other thereover; said bus being configured to receive snoop requests from an originating snooping master, deliver received snoop requests to query other non-originating snooping masters, and communicate snoop results from the non-originating snooping masters back to the originating snooping master; at least two of said snooping masters having snoopable cache memory, any of which can be marked as updated; main memory attached to and in communication with said bus having storage for all data and addresses associated therewith used by all of said snooping masters; logic to collect all designated non-originating responses and create a non-speculative snoop mask to select which other non-originating snooping master or masters which have updated data to snoop for a given address, said bus including logic to direct snoop requests to only the non-originating snooping masters as enabled by a snoop mask, and to return to the originating snooping master directly or indirectly, or to the main memory, or both, any updated data from a non-originating snooping master, and thereafter end snooping without checking validity of the snoop mask and data.
 2. The invention as defined in claim 1 wherein the snoop mask allows a snooping request to be delivered only to non-originating masters.
 3. The invention as defined in claim 1 wherein said logic in the bus includes logic for writing to said originating snooping master requested data from main memory if no updated data is found in any of the non-originating queried snooping masters.
 4. The invention as defined in claim 1 wherein only one snooping master has cache memory that can be marked as updated.
 5. The invention as defined in claim 2 wherein the logic to create snoop masks resides in each originating snooping master.
 6. The invention as defined in claim 1 wherein said logic on said bus includes logic to write updated data to both the originating snooping master and the main memory.
 7. The invention as defined in claim 1 wherein the updated data is returned to the originating master indirectly by writing the data first to the main memory, and then from main memory to the originating snooping master.
 8. The invention as defined in claim 1 wherein the updated data is returned directly to the originating snooping master.
 9. The invention as defined in claim 8 wherein said logic on said bus includes logic to write updated data to both the originating snooping master and the main memory. 